MA320002【PDF 69/208 页】MODULE PLUG-IN PIC32 USB OTG

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TABLE 4-21:

PORT A REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L,

PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY (1)

Bits

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

6000

6010

6020

TRISA

PORTA

LATA

31:16

15:0

31:16

15:0

31:16

15:0

—

TRISA15

—

RA15

—

LATA15

—

TRISA14

—

RA14

—

LATA14

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

TRISA10

—

RA10

—

LATA10

—

TRISA9

—

RA9

—

LATA9

—

—

—

—

—

—

—

TRISA7

—

RA7

—

LATA7

—

TRISA6

—

RA6

—

LATA6

—

TRISA5

—

RA5

—

LATA5

—

TRISA4

—

RA4

—

LATA4

—

TRISA3

—

RA3

—

LATA3

—

TRISA2

—

RA2

—

LATA2

—

TRISA1

—

RA1

—

LATA1

—

TRISA0

—

RA0

—

LATA0

0000

C6FF

0000

xxxx

0000

xxxx

6030

ODCA

31:16 — —

15:0 ODCA15 ODCA14

—

—

—

—

— — —

— ODCA10 ODCA9

— — — — — — — — —

— ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0

0000

0000

Legend:

Note 1:

x = unknown value on Reset, — = unimplemented, read as ‘ 0 ’. Reset values are shown in hexadecimal.

All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more

information.

TABLE 4-22:

PORT B REGISTERS MAP (1)

Bits

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

6040

6050

6060

TRISB

PORTB

LATB

31:16

15:0

31:16

15:0

31:16

15:0

—

TRISB15

—

RB15

—

LATB15

—

TRISB14

—

RB14

—

LATB14

—

TRISB13

—

RB13

—

LATB13

—

TRISB12

—

RB12

—

LATB12

—

TRISB11

—

RB11

—

LATB11

—

TRISB10

—

RB10

—

LATB10

—

TRISB9

—

RB9

—

LATB9

—

TRISB8

—

RB8

—

LATB8

—

TRISB7

—

RB7

—

LATB7

—

TRISB6

—

RB6

—

LATB6

—

TRISB5

—

RB5

—

LATB5

—

TRISB4

—

RB4

—

LATB4

—

TRISB3

—

RB3

—

LATB3

—

TRISB2

—

RB2

—

LATB2

—

TRISB1

—

RB1

—

LATB1

—

TRISB0

—

RB0

—

LATB0

0000

FFFF

0000

xxxx

0000

xxxx

6070

ODCB

31:16 — — — — — — — — — — — — — — — —

15:0 ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0

0000

0000

Legend:

Note 1:

x = unknown value on Reset, — = unimplemented, read as ‘ 0 ’. Reset values are shown in hexadecimal.

All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more

information.

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